clk_word_size=cycles16, clk_gate=no
Clock Configuration Register
| clk_gate | Gating of sclk 0 (no): Clock gating is disabled 1 (cycles12): Gating after 12 sclk cycles 2 (cycles16): Gating after 16 sclk cycles 3 (cycles20): Gating after 20 sclk cycles 4 (cycles24): Gating after 24 sclk cycles |
| clk_word_size | The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode 0 (cycles16): 16 sclk cycles 1 (cycles24): 24 sclk cycles 2 (cycles32): 32 sclk cycles |
| align_mode | Alignment mode setting 1 (standard): Standard I2S format 2 (right): Right aligned format 4 (left): Left aligned format |
| dma_tx_en | DMA transmit enable control |
| dma_rx_en | DMA receive enable control |
| dma_divide_16 | Split 32bit data to two 16 bit data and filled in left and right channel. Used with dma_tx_en or dma_rx_en |
| sign_expand_en | SIGN_EXPAND_EN |